1. Field of the Invention
The present invention relates to a tunnel field-effect transistor (TFET) and a method of fabrication therefor.
2. Background of the Invention
Complementary metal-oxide semiconductor (CMOS) technology is used in high-speed switching and logic applications. A drawback associated with CMOS-based devices in, for example, logic applications is that device-scaling in the sub-65 nm regime is limited, not by the intrinsic switching speeds of such devices, but rather by the magnitude of the power that they dissipate. The semiconductor industry has been engaged in seeking a successor to CMOS that has relatively lower power dissipation compared to CMOS and that may be used in logic applications. For devices in which a logic state is represented by charge, it is known that a reduction in power dissipation may be attained by a reduction in an operating voltage and/or a reduction in a loading capacitance. In this regard, the tunnel field effect transistor (TFET) may be operated at relatively lower operating voltages due to its potential for the sub-kT/Q sub-threshold slope. This has the corresponding result that TFETs have a reduced power dissipation compared to previously-proposed devices such as, for example, CMOS field-effect transistors (FETs), thus making TFETs a promising successor to traditional CMOS. Some examples of single-gated TFETs may be found at U.S. Pat. No. 7,812,370B2 and US2010/0200916A1.
TFETs have some properties which are in contrast to, for example, CMOS-based devices such as metal-oxide semiconductor field-effect transistors (MOSFETs), and which may serve to limit their use in logic applications. For instance, it is known that TFETs are inherently ambipolar in terms of gate bias, that is, current is conducted for the application of a positive or a negative gate bias. This may be undesirable, particularly in logic applications, where it is preferable that the “ON” and “OFF” states of a device are distinct. In this regard, steps may be taken to make the TFET increasingly unipolar, that is, impeding current conduction for one of the gate polarities, such steps including, for example, the use of doping differentiation, heterostructures, or a gate underlap. Furthermore, the asymmetric “p-i-n” structural implementation of the TFET is in contrast to that of the MOSFET, which is implemented in one of the “n-p-n” or “p-n-p” modes. This structural asymmetry of the TFET may pose some problems for its implementation in certain types of logic applications, such as, for example, pass-gate logic used in SRAM (static random access memory).
US2009/0101975A1 discloses an integrated circuit including: a first connection region disposed in a semiconductor body, the first connection region being of a first doping type, an adjacent region disposed in the semiconductor body adjoining the first connection region, the adjacent region being either doped or undoped in accordance with a second doping type, the second doping type being different from the first doping type, an electrically insulating first insulation region disposed at a boundary between the first connection region and adjacent region, and a first control region adjoining the insulation region. This document discloses an integrated semiconductor circuit including: a TFET with an associated gate formed substantially over the channel region of the TFET and a planar FET with a gate associated thereto, with the TFET and the planar FET being laterally disposed relative to each other. The gate dielectric associated with the TFET is chosen to be thicker than the gate dielectric associated with the planar FET, this feature offering the advantage that the gate leakage current and, therefore, the power consumption of the TFET disclosed in US2009/0101975A1 are lower than in previously-proposed devices such as TFETs and/or FETs without this feature.
US2010/0140589A1 discloses a ferroelectric TFET including a ferroelectric gate stack and band-to-band tunnelling in a gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarisation with increasing gate voltage, a positive feedback in the capacitive coupling that controls band-to-band (BTB) tunnelling at the source junction of a silicon p-i-n reversed bias structure, such that the combined effect of the BTB tunnelling and ferroelectric negative capacitance apparently offers more abrupt off-on and on-off transitions compared to previously-proposed TFETs or ferroelectric FETs. This document discloses a ferroelectric TFET including a source-channel-drain structure with two gates being formed on either side of the channel in a perpendicular direction relative to the plane in which the source-channel-drain are disposed.
Turning to WO2010/010944A1, this document discloses a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits, which is concerned with solving the problem of the speed performance limit of an ultra-large scale integration and an ultra low-power consumption type logical circuit. The complementary logical gate disclosed in this document includes an electron running layer formed from graphene without using an n-channel or a p-channel FET, has the ambipolar characteristic and uses only two FETs having different threshold values, i.e. a first FET and a second FET.
US2008/0312088A1 discloses a field-effect transistor including: an ambipolar layer including a source region, a drain region and a channel region between the source region and the drain region, wherein the source region, the drain region and the channel region are formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other. In a multi-gated configuration of the device disclosed in US2008/0312088A1, the gate electrode includes a first gate electrode and a second gate electrode that are respectively formed close to the source region and the drain region above the channel region, wherein when a voltage is selectively applied to the first gate electrode or the second gate electrode, the FET is of an n-type or of a p-type. In the device disclosed in this document, the band-gap of the ambipolar layer may be tailored by way of the choice of width of the channel region relative to that of the source region and the drain region in a specific direction.
In EP1901354A1, there is disclosed a TFET including: a source-channel-drain structure including at least one doped source region, at least one doped drain region, and at least one channel region which is situated in between the at least one source region and the at least one drain region, and forming a source-channel interface with the source region and a drain-channel interface with the drain region, a gate electrode which is covering at least part of the at least one source region, at least extending up to the source-channel interface such that there is a finite distance between the end of the gate electrode and the plane of the channel-drain interface, such that there is no coverage by the gate electrode of the drain region. This document also discloses a multi-gated TFET with one gate overlapping the source and the channel, and another gate being formed on the channel close to the drain but with no overlap with the drain. This gates' structure is replicated on the opposite surface of the channel, in a plane perpendicular to that in which the source-channel-drain structure is arranged, such that there are four gates in total. It is disclosed that the device of EP1901354A1 has improved switching speeds whilst gaining a processing advantage due to there being no need for gate-drain alignment. Furthermore, it is stated that the disclosed device has an improved performance on account of the ambipolar behavior thereof being reduced.
Reference is now made to Yang et. al, Rice University Technical Report TREE1002, pages 1-4, which provides a report on ambipolar electronics, and, particularly, discusses the applications of ambipolar devices such as Graphene and CNT (carbon nanotube) devices.
The development of previously-proposed TFETs has been done in order to: improve device performance by, for example, suppressing some of the inherent characteristics of TFETs that are different from those associated with CMOS-based devices, such as, the ambipolar nature of TFETs; improve device switching speeds; and further reduce power dissipation/consumption. Development of TFETs so that they may potentially be applied in diverse logic applications by, for example, harnessing those properties that set it apart from CMOS-based devices has as yet to be addressed.